[armv8] ESL_EL2 분석 - stage2 data abort

아래는 stage2 mmu에서 data abort가 발생했을때 확인된 ESR_EL2 를 분석한 내용이다.

 

ESR (Hexadecimal format, 'q' or 'Q' : Terminate): 0x93830006       2    2    2    1    1     8    4    0    6    2    8    4    0 -----------------------------------------  1001 0011 1000 0011 0000 0000 0000 0110 ----------------------------------------- ==============================================================    Exception from a Data Abort from a lower exception level ============================================================== EC, bits [31:26]: 100100         Exception Class IL, bit [25]:       1                  Instruction Length for synchronous exceptions ISS : 1 1000 0011 0000 0000 0000 0110   ISV, bit [24]:           Instruction syndrome valid 1                                Bits[23:0] of the ISS field holds IMPLEMENTATION DEFINED syndrome information that can be used to provide additional information about the SError interrupt.   SAS, bits [23:22]: 10            Syndrome Access Size SSE, bit [21]: 0                 Syndrome Sign Extend SRT, bits [20:16]: 00011         Syndrome Register transfer SF, bit [15]: 0                  Width of the register accessed by the instruction is Sixty-Four AR, bit [14]: 0                  Acquire/Release VNCR, bit [13]: 0                Indicates that the fault came from use of VNCR_EL2 register by EL1 code SET, bits [12:11]: 00            Synchronous Error Type FnV, bit [10]: 0                 FAR not Valid EA, bit [9]: 0                   External abort type CM, bit [8]: 0                   Cache maintenance S1PTW, bit [7]: 0                For a stage 2 fault, indicates whether the fault was a stage 2 fault on an access made for a stage 1   translation table walk                              stage 2 fault인지, stage 1 fault인지를 구분짓는것이 아닌, table walk 중에 발생한 fault 인지 아닌지를 구별하는 field임 WnR, bit [6]: 0                  Write not Read DFSC, bits [5:0]: 000110                 Data Fault Status Code   참고 : table walk(tablewalk) 란? MMU가 pagetable(tranlation table)을 가지고 오기 위해서 DRAM에 access하는 동작